gdritter repos dlxvm / master assembler / dlx-assembler.py
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dlx-assembler.py @master

dd94c86
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
from sys import stdin, argv

result = []
ARITH = {
    'add': 0x20,
    'and': 0x24,
    'or':  0x25,
    'seq': 0x28,
    'sle': 0x2c,
    'sll': 0x04,
    'slt': 0x2a,
    'sne': 0x29,
    'sra': 0x07,
    'srl': 0x06,
    'sub': 0x22,
    'xor': 0x26,
    'nul': 0x00
    }

OP = {
  'addi': 0x08,
  'andi': 0x0c,
  'beqz': 0x04,
  'bnez': 0x05,
  'j':    0x02,
  'jal':  0x03,
  'jalr': 0x13,
  'jr':   0x12,
  'lhi':  0x0f,
  'lw':   0x23,
  'ori':  0x0d,
  'seqi': 0x18,
  'slei': 0x1c,
  'slli': 0x14,
  'slti': 0x1a,
  'snei': 0x19,
  'srai': 0x17,
  'srli': 0x16,
  'subi': 0x0a,
  'sw':   0x2b,
  'xori': 0x0e,
  'halt': 0x30,
  'pln':  0x31
}

BYTE = 0xff

for line in stdin.readlines():
    op, *rest = line.split()
    if op in ARITH:
        opcode = 0
        funct = ARITH[op]
        type = 'R'
    else:
        opcode = OP[op]
        if op in ('j', 'jal'):
            type = 'J'
        else:
            type = 'I'

    if type == 'R':
        rs, rt, rd = map(int, rest)
        result.append(opcode << 26 |
                      rs << 21 |
                      rt << 16 |
                      rd << 11 |
                      funct)
    elif type == 'I':
        rs, rt, immed = map(int, rest)
        result.append(opcode << 26 |
                      rs << 21 |
                      rt << 16 |
                      (immed & 0xffff))
    else:
        addr = int(rest[0])
        result.append(opcode << 26 |
                      (addr & 0x3ffffff))

with open(argv[1], 'wb') as f:
    for instr in result:
        f.write(bytes([instr >> 0x18,
                       (instr >> 0x10) & BYTE,
                       (instr >> 0x08) & BYTE,
                       instr & BYTE]))